1. Technical Field
The present invention relates to a semiconductor device and a fabricating method thereof, and more particularly to a semiconductor device using a three-dimensional channel and a fabricating method thereof.
2. Description of the Related Art
As one of scaling techniques for increasing the density of integrated circuit devices, a transistor has been proposed, in which a fin- or nanowire-shaped active pattern is formed with a substrate and a gate is then formed on a surface of the active pattern.
Since the transistor uses a three-dimensional (3D) channel, scaling of the multi-gate transistor can be achieved. In addition, current controlling capability can be improved and a short channel effect (SCE), in which an electric potential of a channel region is affected by a drain voltage, can be effectively suppressed.